The present disclosure relates generally to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a NAND flash memory device having 3-dimensionally arranged memory cells.
A claim of priority under 35 U.S.C. § 119 is made to Korean Patent Application No. 2006-99015, filed on Oct. 11, 2006, the entire contents of which are hereby incorporated by reference.
Most modern electronic appliances include semiconductor devices. These semiconductor devices include a number of elements. Specifically, these semiconductor devices include electronic elements such as, for example, transistors, resistors, capacitors, or the like. Beneficially, these electronic elements are integrated on a semiconductor substrate after they are designed to perform specific functions for the electronic appliances. For example, electronic appliances such as computers and digital cameras include memory chips for storing information and processing chips for processing information. These memory chips and processing chips include electronic elements that are integrated on the semiconductor substrate after being configured to perform information storing and processing functions, respectively.
In order to keep up with customer demand for low price, more efficient, and smaller size devices, there is a growing need for highly integrated semiconductor devices. However, there are certain shortcomings in the semiconductor manufacturing process that affect the availability of highly integrated semiconductor devices. For example, there is a need for advancement in processing technologies such as, for example, lithography technology. However, advanced processing technologies require the expenditure of large amount of capital and may be stuck in research and development cycles for a long time before they are commercially viable for the manufacture of highly integrated semiconductor devices.
In order to work around the restrictions placed by current manufacturing technology, there have been proposals to use 3-dimensionally arranged transistors in semiconductor devices. For example, Korean Patent Application No. 2006-73858 discloses a NAND flash memory device having 3-dimensionally arranged transistors. Such a method of fabricating the semiconductor device includes forming single crystal semiconductor layer(s) on a wafer used as a semiconductor substrate through an epitaxial technology, and thereafter forming transistors on the semiconductor layer(s).
Furthermore, when source and drain electrodes of memory cell transistors are three dimensionally arranged, plugs connecting these source and drain electrodes are needed for electrically accessing the memory cell transistors. However, it may not be easy to form these plugs in three dimensional semiconductor devices. For example, in the NAND flash memory device disclosed in Korean Patent Application No. 2006-73858, the memory transistors formed on different layers are electrically connected to each other through stacked plugs and local interconnections that are formed through different processes.
There may be many problems associated with the use of different processes to fabricate the 3-dimensional semiconductor device. These problems may include, for example the increasing complexity of the over all fabrication process and the increase in fabrication cost. The complexity of a semiconductor device may be reduced by decreasing the chip area available. However, the loss of chip area availability may reduce the integration density of the semiconductor device. This feature is contrary to one of the important objectives of a 3-dimensional semiconductor device.